1. Field of the Invention
The present invention relates to a register device which is employed in a semiconductor storage apparatus such as a FIFO memory to temporarily store data.
2. Description of the Background Art
A FIFO memory constituting field memory is required to be capable of operating at high speed and to have a large capacity in order to handle image data. Consequently, such a FIFO memory is provided with a dynamic memory cell with which high integration is possible and a register device constituted of a write data register and a read data register which temporarily stores specific data.
FIG. 8 illustrates a conventional FIFO memory 101. This FIFO memory 101 is provided with n data input terminals Din-1 through Din-n through which n sets of serial data are respectively input, for instance, and these data input terminals are connected with n data input buffers 111-1 through 111-n respectively. The data input buffers 111-1 through 111-n are circuits that are set in an active state when an H-level signal is input to a write enable terminal WE and input serial data provided through the data input terminals Din-1 through Din-n are respectively input to the data input buffers 111-1 through 111-2. In addition, the output terminals of the data input buffers 111-1 through 111-n are connected with a register device 121 via a write data bus WDB.
The register device 121, which has a function of temporarily storing data from the write data bus WDB, is constituted of n write register units 123-1 through 123-n and n read register units 125-1 through 125-n. The read register units 125-1 through 125-n are connected with a read data bus RDB.
The output terminals of the register device 121 are connected with n data registers 131-1 through 131-n. The data registers 131-1 through 131-n are circuits that are set in an active state when an H-level signal is input to the write enable terminal WE, store data from the register device 121 and output the data to n memory cell arrays 141-1 through 141-n respectively. Each of the memory cell arrays 141-1 through 141-n is provided with a plurality of word lines (not shown) and bit lines (not shown) and memory cells for data storage are arrayed at points where they intersect. It is to be noted that the selection of word lines is selected by an X decoder 142.
The memory cell arrays 141-1 through 141-n are connected with n data registers 151-1 through 151-n respectively. The data registers 151-1 through 151-n enter an active state when an H-level signal is input to the read enable terminal RE and have a function of storing data read out from the memory cell arrays 141-1 through 141-n respectively. The output terminals of the data registers 151-1 through 151-n are respectively connected with n data output buffers 161-1 through 161-n. In addition, the output buffers 161-1 through 161-n are also connected with the read data bus RDB. The data output buffers 161-1 through 161-n enter an active state when an H-level signal is input to the read enable terminal RE and have a function of inputting the data from the data registers 151-1 through 151-n respectively or the data from the read data bus RDB to output them to data output terminals Dout-1 through Dout-n respectively.
The FIFO memory 101 is further provided with a serial write timing control circuit 171 that controls the data write operation based upon a clock signal input through a serial write clock terminal SWCK, with its output terminal connected to a write reset control circuit 173 and the data registers 131-1 through 131-n. The output terminal of the write reset control circuit 173, which is a circuit for resetting the data write operation based upon a reset signal input through a reset write terminal RSTW, is connected to the data registers 131-1 through 131-n.
In addition, in correspondence to the serial write timing control circuit 171 and the write reset control circuit 173, a serial read timing control circuit 175 and a read reset control circuit 177 are respectively provided. The output terminal of the serial read timing control circuit 175, which is a circuit for controlling data read operation based upon a clock signal input through a serial read clock terminal SRCK, is connected to the read reset control circuit 177 and the data registers 151-1 through 151-n. The output terminal of the read reset control circuit 177 which is a circuit for resetting the data read operation based upon the reset signal input through a reset read terminal RSTR is connected to the data registers 151-1 through 151-n.
Furthermore, a clock oscillator 181 for generating a clock signal is provided at the FIFO memory 101, with its output terminal connected to a read/write/refresh control circuit 183. The read/write/refresh control circuit 183 implements read/write control and refresh control for the X decoder 142 based upon outputs from the clock oscillator 181 and the data registers 131-1 through 131-n and 151-1 through 151-n.
Next, the register device 121 provided in the FIFO memory 101 described above is explained in reference to FIG. 9.
The register device 121 is constituted of n sub-register devices SR-1 through SR-n having almost identical functions and structural features. The individual sub-register devices SR-1 through SR-n are respectively provided with the write register units 123-1 through 123-n and the read register units 125-1 through 125-n described earlier. It is to be noted that in this explanation, the sub-register device SR-1 is described as a typical example.
As illustrated in FIG. 9, the sub-register device SR-1 is provided with the write register unit 123-1 connected to the write data bus WDB and the read register unit 125-1 connected to the read data bus RDB. In addition, the write register unit 123-1 and the read register unit 125-1 are connected with each other through a data transfer gate TG constituted of two N channel type transistors.
The write register unit 123-1 is constituted of a write register WR for storing data from the write data bus WDB and a write pointer WP for connecting the write register WR with the write data bus WDB. It is to be noted that the write register WR is constituted of a so-called inverter latch that comprises two inverters. In addition, the write pointer WP is constituted of two N channel type transistors. The write pointers WP provided in the individual sub-register devices SR-1 through SR-n are sequentially set to an ON state by means for shifting such as a shift register (not shown) to connect the write registers WR provided at the individual sub-register devices SR-1 through SR-n with the write data bus WDB. Thus, specific data are sequentially written in the individual write registers WR.
The read register unit 125-1 comprises a read register RR for storing data transferred from the write register 123-1 and a read pointer RP for connecting the read register RR to the read data bus RDB. It is to be noted that the read register RR is constituted of a so-called inverter latch comprising two inverters as in the case with the write register WR. In addition, the read pointer RP is constituted of two N channel type transistors, as in the case with the write pointer WP. The read pointers RP provided at the individual sub-register devices SR-1 through SR-n are sequentially set to an ON state by a means for shifting such as a shift register (not shown) to connect the read registers RR provided at the individual sub-register devices SR-1 through SR-n with the read data bus RDB. As a result, the specific data stored at the individual read registers RR are sequentially output to the read data bus RDB.
In addition, the data transfer gate TG which connects the write register unit 123-1 and the read register unit 125-1 engages in an ON/OFF operation in response to a transfer signal ST provided by a transfer signal generating unit 191. The transfer signal generating circuit 191 outputs an H-level transfer signal ST at a point in time at which, for instance, all the read register units 123-1 through 123-n have completed a read operation and all the write register unit 125-1 through 125-n have completed a write operation, to set the data transfer gates TG provided in all the sub-register devices SR-1 through SR-n in an ON state.
Now, when the FIFO memory 101 is employed in processing a large volume of data, the number of sub-register devices SR-1 through SR-n in the register device 121 illustrated in FIG. 9 will be, for instance, approximately 70 through 100. In the register device 121 in the prior art provided with a large number of the sub-register devices SR-1 through SR-n as in this case, the transfer signal ST output by the transfer signal generating unit 191 may become attenuated while it travels from the sub-register device SR-n located closest to the transfer signal generating unit 191 to reach the sub-register device SR-1 located furthest from the transfer signal generating unit 191, as illustrated in FIG. 10, due to the influence of the capacity capacitative component and the like of the data transfer gates TG in the sub-register devices SR-1 through SR-n. Such attenuation of the transfer signal ST leads to a defective operation of the data transfer gates TG, which poses a problem that the data at the write register unit 123-1 may not be correctly transferred to the read register unit 125-1.
Furthermore, if the data stored at the write register units 123-1 through 123-n do not match the data stored at the corresponding read register units 125-1 through 125-n, all the inverters constituting the individual read registers RR will perform an inversion operation at once, which may result in a reduction in the source potential Vcc or an increase in the ground potential Gnd, as illustrated in FIG. 10. Large fluctuations in the source potential Vcc and the ground potential Gnd not only induce a defective operation of the transfer gates TG but also adversely affect the circuits other than the register device 121.